1. Field of the Invention
The present invention relates to a chip package and an electrical connection structure between a chip and a substrate. More particularly, the present invention relates to a high performance chip package and electrical connection structure between a chip and a substrate.
2. Description of the Related Art
In an information society, everybody is searching for high speed, high quality and multifunctional electronic products. Other criteria for selecting a particular product may also include aesthetic appeal, weight and size. Most electronic products typically enclose a semiconductor chip and a carrier for electrically connecting with the semiconductor chip. At present, there are three major techniques for connecting a chip to a carrier, namely, a wire-bonding process, a flip-chip process and a tape-automated-bonding (TAB) process. If the carrier is a lead frame, the wire-bonding process is often used to connect the chip with the leads on the lead frame.
The quality of signal transmission between a chip and surrounding lead frame is frequently affected by minor difference in impedance between the bonded wires and the system. Any difference in wire impedance and system impedance may cause an impedance mismatch that results in signal reflection. If the impedance of the bonded wire is greater than the system impedance, a positive phase signal will be reflected. Conversely, if the impedance of the bonded wire is smaller than the system impedance, a negative phase signal will be reflected. Ideally, there is no signal reflection and it occurs when the impedance of the bonded wire matches the system impedance exactly. However, if the impedance mismatch between the bonded wires and the system is really large, the semiconductor chip may produce some computation errors.
FIG. 1A is a schematic cross-sectional view of a conventional chip package with a chip electrically connected to a lead frame using a wire-bonding process. FIG. 1B is a perspective view of the electrical connection structure between a chip and a substrate shown in FIG. 1A. As shown in FIGS. 1A and 1B, the chip package 100 comprises a chip 110, a lead frame 120, signal wires 130a, ground wires 130b and an insulation material 150. The lead frame 120 has a die pad 122 and a plurality of identical leads 124. The leads 124 are distributed evenly at the peripheral area of the die pad 122. The chip 110 is attached to the die pad 122 through adhesive glue 172. The signal wires 130a and the ground wires 130b connecting the chip 110 to the respective leads 124a and 124b are formed in a wire-bonding process. The die pad 122 and the lead 124b are electrically connected through pad 194 on a substrate 190 to provide an electrical ground. The insulation material 150 encapsulates the chip 110, the lead frame 120, the signal wires 130a and the ground wires 130b. The die pad 122 and the leads 124 of the chip package 100 are attached to the substrate 190 through the application of adhesive materials 174 and 176.
As shown in FIG. 1B, the chip 110 is electrically connected to the pad 192 of the substrate 190 through signal wires 130a, the leads 124a and the adhesive material 176. The ground wire 130b is located at both sides of the signal wire 130a to serve as an electrical shield. The ground wires 130b not only minimizes external electrical interference to the signal wire 130a during signal transmission, but also prevents the signal wire 130a from causing interference to other wires. Because each signal wire 130a has a small cross-sectional area and a long length, relatively high impedance is produced during high frequency signal transmission. When the impedance of the signal wire 130a deviates significantly from the system impedance, serious signal reflection occurs and the probability of producing computation errors in the chip 110 increases considerably.
FIG. 2A is a schematic cross-sectional view of another conventional chip package with a chip electrically connected to a lead frame using a wire-bonding process. FIG. 2B is a perspective view of the electrical connection structure between a chip and a substrate shown in FIG. 2A. The chip package is almost identical to the one in FIGS. 1A and 1B except for the bonding of additional ground wires 140 linking the chip 110 and the die pad 122.